USB 2.0-USB-IF high speed certified (TID # 40440111) Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor Fit, form and function compatible with the FX2 Pin-compatible Object-code-compatible Functionally-compatible (FX2LP is a superset) Ultra Low power: ICC no more than 85 mA in any mode Ideal for bus and battery powered applications Software: 8051 code runs from: Internal RAM, which is downloaded via USB Internal RAM, which is loaded from EEPROM External memory device (128 pin package) 16 KBytes of on-chip Code/Data RAM Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints Buffering options: double, triple, and quad Additional programmable (BULK/INTERRUPT) 64-byte endpoint 8- or 16-bit external data interface Smart Media Standard ECC generation GPIF (General Programmable Interface) Allows direct connection to most parallel interface Programmable waveform descriptors and configuration registers to define waveforms Supports multiple Ready (RDY) inputs and Control (CTL) outputs Integrated, industry-standard enhanced 8051 48-MHz, 24-MHz, or 12-MHz CPU operation Four clocks per instruction cycle Two USARTS Three counter/timers Expanded interrupt system Two data pointers 3.3V operation with 5V tolerant inputs Vectored USB interrupts and GPIF/FIFO interrupts Separate data buffers for the Set-up and Data portions of a CONTROL transfer Integrated I2C controller, runs at 100 or 400 kHz Four integrated FIFOs Integrated glue logic and FIFOs lower system cost Automatic conversion to and from 16-bit buses Master or slave operation Uses external clock or asynchronous strobes Easy interface to ASIC and DSP ICs