Packet Header Search Solution (100G)
详情介绍
Overview
IoT era has arrived. With the exploding number of “things” connected to the internet and the realtime feedback requirements of these devices, demands of much higher speed network system are getting bigger year after year. As the industry migrates to 100Gb traffic, high power consumption of tradition search engine solution becomes a huge problem for data center networks. Renesas produced a low power search solution for higher packet forwarding that grows with your network.
Renesas Exact Match reference design includes proprietary search algorithm, LLDRAM-III control IP on a FPGA host controller, accompanied by a suite of development tools.
Key features of Exact Match Refernce Design.
- 1) Lookup over one million rules of packet headers for 100Gb network system in around 2 watts, which means Quantity of Memory Devices to 1/15th and 60% Cut in Memory Power Consumption. *
- 2) Scale with future network protocols by flexible configuration of search key length of up to 575bits.
- 3) Reduce network systems development cycle time by providing an all-in-one development platform with an on board Xilinx FPGA and LLDRAM-III
*If MAC address lookup at 150 million search per second
System Block Diagram
Recommended Products
| Block | Semiconductor device | Recommended products | Features, etc. |
|---|---|---|---|
| Network memory | DRAM | RMHE41A364AGBG (LLDRAM-III) |
Related Documents
| Document Title | Document No. |
|---|---|
| Exact Match Search Solution White Paper | R10AN0010EJ0200 |
| Control IP White Paper | R10AN0011EJ0100 |
Evaluation System
Improve time-to-market by utilizing proven evaluation system for product development
Evaluation system includes:
- Reference board with onboard FPGA and LLDRAM III
- Sample design with Search Engine IP
- Verification and evaluation applications
Item list for evaluation system
| Items | Content |
|---|---|
| Documents | Quick Start Guide, Exact Match Search IP Design Guide, PCB Design Guide, GUI Software Guide, API Guide, LLDRAM-III data sheet |
| Exact Match Search IP（as a reference design） | Verilog Source Code, AXI4 Slave Bridge Module |
| LLDRAM-III model | Verilog Behavior Model, IBIS Model |
| Sample design | Verilog Source Code, FPGA Implementation Environment, Logic Simulation Environment（VCS /Modelsim）, GUI Software |
| API for table maintenance | ANSI-C Source Code |
| Reference board | Interoperability verified between FPGA and LLDRAM-III |
To inquire about Renesas Evaluation system, please contact us here.