| Number of Channels per Chip | 8 |
| Fabrication Technology | CMOS |
| Input Level | LVTTL|TTL |
| Max Processing Temp | 260 |
| Output Type | 3-State |
| Number of Elements per Chip | 1 |
| Tolerant I/Os | 5 V |
| SCHEDULE B | 8542310000 |
| Screening Level | Commercial |
| Data Flow Direction | Bi-Directional |
| Logic Function | Bus Transceiver with Voltage Translation |
| Typical Operating Supply Voltage | 1.8|2.5|3.3|5 V |
| Polarity | Non-Inverting |
| Propagation Delay Test Condition | 15 pF |
| Output Level | LVCMOS |
| Operating Temperature | -40 to 85 °C |
| UNSPSC VERSION | V15.1101 |
| Maximum Low Level Output Current | 32 mA |
| Maximum High Level Output Current | -32 mA |
| Maximum Operating Supply Voltage | 5.5 V |
| ECCN | EAR99 |
| Lead Finish | Gold |
| Maximum Quiescent Current | 15 uA |
| Mounting | Surface Mount |
| Minimum Operating Supply Voltage | 1.65 V |
| Number of Output Enables per Element | 1 Low |
| Maximum Propagation Delay Time @ Maximum CL | 23.8@1.8V ns |
| Bus Hold | No |
| UNSPSC | 32101654 |
| Number of Direction Control Inputs | 1 Low/High |
