| Number of Channels per Chip | 4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 27@5V |
| PCB changed | 16 |
| Number of Elements per Chip | 2 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Temperature (°C) | 70 |
| Supplier Package | PDIP |
| Maximum High Level Output Current (mA) | -0.4 |
| Latch Mode | Transparent |
| Process Technology | Bipolar |
| Absolute Propagation Delay Time (ns) | 30 |
| Propagation Delay Test Condition (pF) | 15 |
| Package Height | 5.08(Max) - 0.51(Min) |
| Polarity | Inverting/Non-Inverting |
| Maximum Operating Supply Voltage (V) | 5.25 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 0 |
| Set/Reset | No |
| Number of Inputs per Chip | 4 |
| Number of Outputs per Chip | 4 |
| Supplier Temperature Grade | Commercial |
| Package Length | 19.69(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 8 |
| Pin Count | 16 |
| Mounting | Through Hole |
| Type | D-Type |
| Number of Output Enables per Element | 0 |
| Number of Input Enables per Element | 1 |
| Bus Hold | No |
| Lead Shape | Through Hole |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5 |
| Logic Family | LS |
| Package Width | 6.6(Max) |
| Minimum Operating Supply Voltage (V) | 4.75 |
