| Maximum Propagation Delay Time @ Maximum CL (ns) | 35@4.5V|30@6V|175@2V |
| PCB changed | 14 |
| HTS | 8542.39.00.01 |
| Number of Elements per Chip | 1 |
| ECCN (US) | EAR99 |
| Parallel Enable Input | No |
| Number of Stages | 8 |
| Direction Type | Uni-Directional |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | PDIP |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 255 |
| Propagation Delay Test Condition (pF) | 50 |
| Logic Function | Shift Register |
| Number of Count Input Enables | 0 |
| Triggering Type | Positive-Edge |
| Package Height | 5.08(Max) - 0.51(Min) |
| Number of Element Outputs | 8 |
| Maximum Operating Supply Voltage (V) | 6 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 0 |
| Number of Element Inputs | 2 |
| Package Length | 19.69(Max) |
| Terminal Count Output | No |
| Standard Package Name | DIP |
| Operation Mode | Serial to Parallel |
| Pin Count | 14 |
| Mounting | Through Hole |
| Reset Type | Asynchronous |
| Lead Shape | Through Hole |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5 |
| Logic Family | HC |
| Package Width | 6.6(Max) |
| Minimum Operating Supply Voltage (V) | 2 |
