| Number of Channels per Chip | 2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 28@6V|32@4.5V|160@2V |
| PCB changed | 14 |
| HTS | 8542.39.00.01 |
| Number of Elements per Chip | 2 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | PDIP |
| Maximum High Level Output Current (mA) | -5.2 |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 240 |
| Propagation Delay Test Condition (pF) | 50 |
| Logic Function | JK-Type |
| Triggering Type | Negative-Edge |
| Package Height | 5.08(Max) - 0.51(Min) |
| Number of Element Outputs | 1 |
| Polarity | Inverting/Non-Inverting |
| Maximum Operating Supply Voltage (V) | 6 |
| EU RoHS | Compliant |
| Set/Reset | Reset |
| Number of Element Inputs | 2 |
| Package Length | 19.69(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 5.2 |
| Pin Count | 14 |
| Mounting | Through Hole |
| Input Signal Type | Single-Ended |
| Bus Hold | No |
| Lead Shape | Through Hole |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5|3.3|2.5 |
| Logic Family | HC |
| Package Width | 6.6(Max) |
| Maximum Quiescent Current (mA) | 0.004 |
| Minimum Operating Supply Voltage (V) | 2 |
