| Maximum Propagation Delay Time @ Maximum CL (ns) | 20@4.5V|17@6V|100@2V |
| PCB changed | 14 |
| Output Type | Open Drain |
| Maximum Quiescent Current (uA) | 2 |
| Number of Elements per Chip | 4 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | PDIP |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 150 |
| Propagation Delay Test Condition (pF) | 50 |
| Logic Function | NAND |
| Package Height | 5.08(Max) - 0.51(Min) |
| Number of Element Outputs | 1 |
| Maximum Operating Supply Voltage (V) | 6 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 0 |
| Number of Element Inputs | 2-IN |
| Supplier Temperature Grade | Military |
| Package Length | 19.69(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 5.2 |
| Pin Count | 14 |
| Mounting | Through Hole |
| Number of Output Enables per Element | 0 |
| Lead Shape | Through Hole |
| Part Status | Obsolete |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5|3.3|2.5 |
| Logic Family | HC |
| Package Width | 6.6(Max) |
| Minimum Operating Supply Voltage (V) | 2 |
