Maximum Propagation Delay Time @ Maximum CL (ns) | 500@5V|150@15V|200@10V |
PCB changed | 16 |
HTS | 8542.39.00.01 |
Number of Elements per Chip | 1 |
ECCN (US) | EAR99 |
Parallel Enable Input | No |
Number of Stages | 5 |
Direction Type | Uni-Directional |
Minimum Operating Temperature (°C) | -55 |
Maximum Operating Temperature (°C) | 125 |
Supplier Package | PDIP |
Process Technology | CMOS |
Absolute Propagation Delay Time (ns) | 600 |
Propagation Delay Test Condition (pF) | 50 |
Logic Function | Counter/Divider |
Number of Count Input Enables | 2 |
Triggering Type | Positive-Edge |
Package Height | 5.08(Max) - 0.51(Min) |
Number of Element Outputs | 7 |
Maximum Operating Supply Voltage (V) | 18 |
EU RoHS | Compliant |
Number of Selection Inputs per Element | 0 |
Number of Element Inputs | 1 |
Package Length | 19.69(Max) |
Terminal Count Output | Yes |
Standard Package Name | DIP |
Operation Mode | UP Counter |
Pin Count | 16 |
Mounting | Through Hole |
Type | Decade |
Lead Shape | Through Hole |
Part Status | Active |
Packaging | Tube |
Typical Operating Supply Voltage (V) | 12|15|5|3.3|9 |
Logic Family | CD4000 |
Package Width | 6.6(Max) |
Maximum Quiescent Current (mA) | 0.1 |
Minimum Operating Supply Voltage (V) | 3 |