| Maximum Propagation Delay Time @ Maximum CL (ns) | 120@10V|250@5V|90@15V |
| PCB changed | 14 |
| Maximum Quiescent Current (uA) | 5 |
| Number of Elements per Chip | 3 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | PDIP |
| Maximum High Level Output Current (mA) | -4.2(Min) |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 250 |
| Propagation Delay Test Condition (pF) | 50 |
| Logic Function | NOR |
| Package Height | 5.08(Max) - 0.51(Min) |
| Number of Element Outputs | 1 |
| Maximum Operating Supply Voltage (V) | 18 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 0 |
| Typical Quiescent Current (uA) | 0.02 |
| Number of Element Inputs | 3-IN |
| Package Length | 19.69(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 4.2(Min) |
| Pin Count | 14 |
| Mounting | Through Hole |
| Number of Output Enables per Element | 0 |
| Lead Shape | Through Hole |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 12|15|5|3.3|9 |
| Logic Family | CD4000 |
| Package Width | 6.6(Max) |
| Minimum Operating Supply Voltage (V) | 3 |
