| Number of Channels per Chip | 2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 21@4.5V to 5.5V |
| PCB changed | 16 |
| Number of Elements per Chip | 2 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | CDIP |
| Maximum High Level Output Current (mA) | -0.4 |
| Process Technology | Bipolar |
| Absolute Propagation Delay Time (ns) | 21 |
| Propagation Delay Test Condition (pF) | 50 |
| Logic Function | JK# -Type |
| Triggering Type | Positive-Edge |
| Package Height | 3.56(Max) |
| Number of Element Outputs | 1 |
| Polarity | Inverting/Non-Inverting |
| Maximum Operating Supply Voltage (V) | 5.5 |
| EU RoHS | Not Compliant |
| Set/Reset | Set/Reset |
| Number of Element Inputs | 2 |
| Supplier Temperature Grade | Military |
| Package Length | 21.34(Max) |
| Standard Package Name | DIP |
| Maximum Low Level Output Current (mA) | 4 |
| Pin Count | 16 |
| Mounting | Through Hole |
| Input Signal Type | Single-Ended |
| Bus Hold | No |
| Lead Shape | Through Hole |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5 |
| Logic Family | ALS |
| Package Width | 7.62(Max) |
| Minimum Operating Supply Voltage (V) | 4.5 |
