| Number of Channels per Chip | 2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 0.5@3V to 5.5V |
| PCB changed | 20 |
| Number of Elements per Chip | 2 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 85 |
| Supplier Package | QFN EP |
| Maximum High Level Output Current (mA) | -50 |
| Process Technology | ECL |
| Absolute Propagation Delay Time (ns) | 0.575 |
| Logic Function | D-Master-Slave Type |
| Triggering Type | Positive-Edge/Negative-Edge |
| Package Height | 0.95(Max) |
| Number of Element Outputs | 1 |
| Polarity | Inverting/Non-Inverting |
| Maximum Operating Supply Voltage (V) | -5.5|5.5 |
| EU RoHS | Compliant |
| Set/Reset | Set/Reset |
| Number of Element Inputs | 1 |
| Package Length | 4 |
| Standard Package Name | QFN |
| Maximum Low Level Output Current (mA) | 50 |
| Pin Count | 20 |
| Mounting | Surface Mount |
| Input Signal Type | Differential |
| Bus Hold | No |
| Lead Shape | No Lead |
| Part Status | Active |
| Packaging | Tube |
| Typical Operating Supply Voltage (V) | 5|-5|3.3|-3.3 |
| Logic Family | ECL |
| Package Width | 4 |
| Minimum Operating Supply Voltage (V) | 3|-3 |
