| Number of Channels per Chip | 8 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 39@4.5V |
| PCB changed | 16 |
| Maximum Quiescent Current (uA) | 8 |
| Number of Elements per Chip | 1 |
| ECCN (US) | EAR99 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 125 |
| Supplier Package | SSOP |
| Maximum High Level Output Current (mA) | -4 |
| Latch Mode | Addressable |
| Process Technology | CMOS |
| Absolute Propagation Delay Time (ns) | 62 |
| Propagation Delay Test Condition (pF) | 50 |
| Package Height | 1.8(Max) |
| Polarity | Non-Inverting |
| Maximum Operating Supply Voltage (V) | 5.5 |
| EU RoHS | Compliant |
| Number of Selection Inputs per Element | 3 |
| Set/Reset | Master Reset |
| Number of Inputs per Chip | 1 |
| Number of Outputs per Chip | 8 |
| Package Length | 6.4(Max) |
| Maximum Low Level Output Current (mA) | 5.2 |
| Pin Count | 16 |
| Mounting | Surface Mount |
| Type | D-Type |
| Number of Output Enables per Element | 0 |
| Number of Input Enables per Element | 1 |
| Bus Hold | No |
| Part Status | Obsolete |
| Packaging | Tape and Reel |
| Typical Operating Supply Voltage (V) | 5 |
| Logic Family | HCT |
| Package Width | 5.4(Max) |
| Minimum Operating Supply Voltage (V) | 4.5 |
